The present invention relates to the protection of a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) fabricated by silicon-on-insulator (SOI) technology.
For protection from electrostatic discharge (ESD), the signal input terminals of CMOS ICs are often connected to internal power-supply lines through internal protective circuit elements that conduct when the input voltage goes above the power-supply voltage, and to internal ground lines through protective elements that conduct when the input voltage goes below the ground level. Electrostatic discharges and other abnormal input surges are thereby shunted to the power-supply or ground before they can damage internal logic circuits.
Some CMOS ICs, however, must be designed to accept input voltages higher than their native power-supply voltage without shunting input current to the power supply. Examples include ICs operating in mixed-voltage systems, and ICs with input specifications that set limits on input current at an input voltage exceeding the specified power-supply voltage. The internal protective elements connecting the signal input terminals to the power-supply lines must be omitted in these ICs, which are therefore at increased risk of gate-oxide damage to transistors on the power-supply side of their CMOS input circuits.
Similarly, there are CMOS ICs that must tolerate input signal voltages below the ground level without shunting input current to ground. In these ICs, the protective elements linking the signal input terminals to the internal ground lines must be omitted. These devices are at increased risk of gate-oxide damage to transistors on the ground side.
In bulk CMOS devices, these increased risks are moderated because the semiconductor substrate, which is of one conductive type, includes numerous wells of the opposite conductive type. The junctions between the substrate and its wells constitute parasitic diodes through which the ground lines are linked to the power-supply lines. If an input surge is conducted by a protective element to the ground lines, for example, the parasitic diodes then conduct the surge to the power-supply lines, so that all electrodes of the CMOS input circuits are at approximately the surge potential, and damage can be avoided.
This safeguard is not present in CMOS ICs fabricated by SOI technology, in which the circuit elements are formed on a layer of insulating material, without wells and their associated parasitic diodes. In an SOI CMOS device, if the input circuits have protective elements only on the ground side, or only on the power-supply side, then gate-oxide damage is liable to occur on the unprotected side.
SOI has significant advantages over bulk CMOS technology, however. One advantage is reduced power consumption, because current leakage into the substrate is substantially eliminated. Another advantage is higher switching speed, because the capacitance of source and drain areas is reduced. For these and other reasons, SOI. CMOS ICs are expected to come into increasing use, and adequate ESD protection must be provided.
An object of the invention is to provide ESD protection for an SOI CMOS IC having an input terminal that is not limited to the voltage range between the native power-supply and ground.
Another object is to provide such protection within the constraints of conventional logic-circuit design.
The invented input protection circuit is disposed in an SOI CMOS IC having an input terminal electrically coupled through an internal input signal line and resistor to the gate electrodes of a CMOS inverter. The CMOS inverter receives a first power-supply potential from a first internal power-supply line, and a second power-supply potential from a second internal power-supply line. The input protection circuit comprises:
a third internal power-supply line electrically coupled to the first internal power-supply line;
a first protective element coupled between the input signal line and the third internal power-supply line; and
a second protective element coupled between the first and second internal power-supply lines.
The input protection circuit may also have a fourth internal power-supply line, electrically coupled to the second internal power-supply line, and a third protective element, coupled between the third and fourth internal power-supply lines.
The voltage at the input terminal is not restricted to the range between the first and second power-supply potentials, because the input signal line is coupled through a protective element to only one internal power-supply line.
Both sides of the CMOS inverter are protected from input surges, however, because the second protective element conducts surge current from one side to the other.
When the third protective element is provided, the second protective element need not be large, and can be laid out within the constraints of conventional logic design.